1. Field
Embodiments of the invention relate to microelectronic devices and their manufacture. In particular, embodiments of the invention relate to microelectronic devices that include etch stop layers selectively formed over a metal gate where the etch stop layers include metal compounds, and to methods of manufacturing such microelectronic devices.
2. Background Information
The size of transistors and the spacing between transistors continues to decrease in an effort to increase device integration density in integrated circuits that are spaced more closely together. As the size of the transistors and the spacing between them decrease, the risk of electrical contact shortings increases.
Electrical contacts are typically created to provide electrical connections to the sources, drains, and gates of the transistors. Typically, lithography techniques are used to define the location of the contact holes for the electrical contacts. Then the contact holes are then filled with a conductive material to form electrical contacts to source, drain, and gate regions of the transistor.
Misalignment or misregistration of the contact holes may potentially occur due in part to resolution limitations of the patterning and lithography tools, imperfections of the wafer processing operations, or combinations of these factors. If misalignment or misregistration occurs, in some cases, the contact hole of a source or drain contact may potentially erroneously be created above the gate of the transistor so that the conductive material may electrically couple with the gate. Such electrical coupling may represent contact-to-gate shorting, which may render the transistor inoperable and tend to reduce wafer yields.
One known way to help reduce the risk of such shorting is to reduce the size of the contact holes. However, this may lead to an increase in contact resistance.
Another know way to reduce the risk of such shorting is to increase the spacing between the source, drain, and gate of the transistor so that fewer misalignments are observed for a given registration capability. However, this approach tends to decrease the number of transistors that can be fabricated on a die or make the die bigger.